8085 microprocessor Multiple Choice Questions (MCQ part 2)

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  1. SP (stack pointer) register holds the
    A. Base address of stack
    B. Address of stack top
    C. Address of the instruction to be fetched
    D. None of these ANSWER: B
  2. What is the address space of 8086 CPU?
    A. One Megabytes
    B. 256 kilobytes
    C. 1 k megabytes
    D. 64 kilobytes
    ANSWER: A
  3. If 8255A chip is selected when A2 to A7 pins are 1, what is the address of Port C?
    A. FC
    B. FD
    C. FB
    D. FE
    ANSWER: D
  4. In 8085 microprocessor, during PUSH/PSW operation, stack pointer is
    A. Decremented by one
    B. Decremented by two
    C. Incremented by one
    D. Incremented by two
    ANSWER: B
  5. In an 8085, which is always the first machine cycle of an instruction?
    A. An op-code fetch cycle
    B. A memory read cycle
    C. A memory write cycle
    D. An I/O read cycle
    ANSWER: A
  6. Which of the following is hardware interrupts?
    A. RST5.5, RST6.5, RST7.5
    B. INTR, TRAP
    C. A & B
    D. None of these
    ANSWER: C
  7. What is the RST for the TRAP?
    A. RST5.5
    B. RST4.5
    C. RST4
    D. RST3
    ANSWER: B
  8. What are level Triggering interrupts?
    A. INTR&TRAP
    B. RST6.5&RST5.5
    C. RST7.5&RST6.5
    D. None of these
    ANSWER: B
  9. What is SIM?
    A. Select Interrupt Mask
    B. Sorting Interrupt Mask
    C. Set Interrupt Mask
    D. Select Internal Memory
    ANSWER: C
  10. RIM is used to check whether, __
    A. The write operation is done or not
    B. The interrupt is Masked or not
    C. A & B
    D. None of these
    ANSWER: B
  11. What is meant by maskable interrupts?
    A. An interrupt which can never be turned off.
    B. An interrupt that can be turned off by the programmer.
    C. None
    D. An interrupt that can be turned off by processor itself.
    ANSWER: B
  12. Which processor structure is pipelined?
    A. All x80 processors
    B. All x85 processors
    C. All x86 processors
    D. A & B
    ANSWER: C
  13. Address line for RST3 is?
    A. 0020H
    B. 0028H
    C. 0018H
    D. 0010H
    ANSWER: C
  14. In 8086 the overflow flag is set when
    A. The sum is more than 16 bits
    B. Signed numbers go out of their range after an arithmetic operation
    C. Carry and sign flags are set during subtraction
    D. None
    ANSWER: B
  15. BHE of 8086 microprocessor signal is used to interface the
    A. Even bank memory
    B. Odd bank memory
    C. I/O
    D. DMA
    ANSWER: B
  16. In 8086 microprocessor the following has the highest priority among all type interrupts
    A. NMI
    B. DIV 0
    C. TYPE 255
    D. OVER FLOW
    ANSWER: B
  17. In 8086 microprocessor one of the following statements is not true
    A. Coprocessor is interfaced in MAX mode
    B. Coprocessor is interfaced in MIN mode
    C. I/O can be interfaced in MAX / MIN mode
    D. Supports pipelining
    ANSWER: B
  18. Address line for TRAP is?
    A. 0023H
    B. 0024H
    C. 0033H
    D. 0034H
    ANSWER: B
  19. The 8051 microcontroller is of pin package as a _ processor.
    A. 30, 1byte
    B. 20, 1 byte
    C. 40, 8 bit
    D. 40, 8 byte
    ANSWER: C
  20. In 8051 the SP is of _ wide register. And this may be defined anywhere in the __.
    A. 8 byte, on-chip 128 byte RAM.
    B. 8 bit, on chip 256 byte RAM.
    C. 16 bit, on-chip 128 byte ROM
    D. 8 bit, on chip 128 byte RAM
    ANSWER: D
  21. In 8051 after reset, SP register is initialized to address________.
    A. 08H
    B. 09H
    C. 07H
    D. 06H
    ANSWER: C
  22. In 8051what is the address range of SFR Register bank?
    A. 00H-77H
    B. 40H-80H
    C. 80H-7FH
    D. 80H-FFH
    ANSWER: D
  23. The address range for bit addressable RAM of the on-chip 128byte RAM in 8051 microcontroller is
    A. 30 to 7F
    B. 18 to 1F
    C. 10 to 17
    D. 20 to 2F
    ANSWER: D
  24. When a subroutine is called, the address of the next instruction following the CALL instruction is stored on the —–
    A. Stack pointer
    B. Accumulator
    C. Program counter
    D. Stack
    ANSWER: D
  25. Which one is the indirect addressing mode in the following instructions?
    A. LXI H 2050 H
    B. MOV A, B
    C. LDAX B
    D. LDA 2050 H
    ANSWER: C
  26. In an instruction of 8085 microprocessor, how many bytes are present?
    A. One or two
    B. One, two or three
    C. One only
    D. Two or three
    ANSWER: B
  27. Cache memory
    A. Increases performance
    B. increases machine cycle
    C. reduces performance
    D. none of these
    ANSWER: A
  28. Associative memory is a
    A. Very cheap memory
    B. pointer addressable
    C. content addressable memory
    D. slow memory
    ANSWER: C
  29. The memory map of a 8 kB memory chip begins at the location E000H. The last location of the
    memory address and number of pages in the chip are
    A. EF00H, 2
    B. F000H, 8
    C. FFFFH, 32
    D. E000H, 16
    ANSWER: C

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